1. Technical Field of the Invention
This invention relates generally to mixed signal circuitry and more particularly to clock circuits.
2. Description of Related Art
As is known, one or more clock circuits are included on integrated circuits to supply clock signals for other circuitry on an integrated circuit (IC). For example, a processing core may use one or more clock signals; memory may use one or more different clock signals, and input/output interfaces may use one or more of the same clock signals or still different clock signals. As another example, radio frequency (RF) circuitry uses one or more variable clock signals to provide one or more variable local oscillations. In the latter example, many RF applications require the local oscillation, and hence the clock signal, to be changed from one rate to another in a very short period of time (e.g., 10 micro-seconds to 10 milli-seconds).
As is further known, a clock circuit may be implemented in a variety of ways. For instance, a clock circuit may be implemented using a phase locked loop (PLL), a fractional-N synthesizer, a counter, a frequency divider, a frequency multiplier, a crystal oscillator, and/or a combination thereof. Of these implementations, a PLL and/or a fractional-N synthesizer are most commonly used to produce clock signals that require a tight tolerance and/or require fast and accurate rate adjustments.
While a PLL works well to provide an accurate and adjustable clock signal, it does have some practical limitations on the adjustability of the rate of the clock signal. For example, if the PLL includes a divider (M) that divides a reference oscillation prior to inputting into a phase detector and further includes a feedback divider (N), then the output oscillation will have a rate of N/M times the rate of the reference oscillation. In this example, if the desired ratio of N/M is a simple ratio (e.g., 3/2, 5/3, 6, etc.), the rate of the PLL and/or reference oscillation generator (e.g., a crystal oscillator) will typically fall in a range easily handled by a PLL. As the desired ratio becomes more complex (e.g., 137/23=5.96), the rate of the PLL and/or reference oscillation generator has to increase. For some ratios, the rate exceeds practical limitations of a PLL and/or reference oscillation generator. In addition, the bandwidth of the PLL limits the granularity of the ratio.
A fractional-N synthesizer provides a clock circuit that allows for fine adjustment of a clock without exceeding practical limitations of a PLL and/or of the reference oscillation generator by including a delta-sigma modulator in the feedback path. For example, if the desired ratio is 5.96, the delta-sigma modulator modulates the feedback divider between 5 and 6 such that, over time, the average feedback divider is 5.96. This approach, however, requires complex circuitry and may create jitter in the clock signal due to the switching between the divider values.
Therefore, a need exists for a clock circuit that can generate an arbitrary rate clock signal without some or all of the above limitations.